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Jeyavijayan Rajendran

New York University
University of Texas at Dallas
Texas A&M University

127

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4021

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Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction.

2022 IEEE Trans. Emerg. Top. Comput.
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TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities.

2022 CoRR
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Guest Editors’ Introduction: Competing to Secure SoCs

2021 IEEE Design & Test of Computers
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Does logic locking work with {EDA} tools?

2021 SECURITY | USENIX Security Symposium
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Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing

2021 IEEE Transactions on Information Forensics and Security
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A Cross-Layer Framework For Cost-Effective Intellectual Property (IP) Protection

2021
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Analog IP Protection and Evaluation

2021
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Organizing The World's Largest Hardware Security Competition: Challenges, Opportunities, and Lessons Learned

2021 GLSVLSI | Great Lakes Symposium on VLSI
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Trustworthy Hardware Design: Combinational Logic Locking Techniques

2020
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Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction

2020 IEEE Transactions on Emerging Topics in Computing
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