PR3: Power Efficient And Low Latency Baseband Processing For LTE Femtocells

Authors:
Nishant Budhdev National University of Singapore, Singapore
Mun Choon Chan National University of Singapore, Singapore
Tulika Mitra NUS Singapore, Singapore

Abstract:

In order to provide greater network capacity, the use of small base stations such as Femtocells has increased to allow higher spectrum reuse. In these Femtocells, base station designers have started to explore the use of general purpose multi-core architectures to provide greater flexibility. Multi-core architectures allow power-performance trade-off possibilities through techniques such as Dynamic Voltage Frequency Scaling (DVFS) and Power Gating. In this work, we propose a power management framework based on reinforcement learning called PR 3 , which uses both DVFS and Power Gating. Our approach is unique as it introduces a feedback from the network scheduler and baseband processor to the Power Governor, so that information about both the network and computation workloads are included in the decision making. Evaluation on a hardware platform (Odroid XU3) running PHY LTE uplink baseband processing benchmark, shows that PR 3 performs well in terms of both power and latency. It is able to save upto 50% power while maintaining low processing latency. PR 3 is also adaptive, making it effective over a wide range of traffic loads.

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