System Architecture Directions For Post-SoC/32-bit Networked Sensors

Authors:
Hyung-Sin Kim UC Berkeley
Michael P Andersen UC Berkeley
Kaifei Chen UC Berkeley
Sam Kumar UC Berkeley
William J. Zhao UC Berkeley
Kevin Ma UC Berkeley
David E. Culler UC Berkeley

Introduction:

The emergence of low-power 32-bit Systems-on-Chip (SoCs) presents an opportunity to re-examine design points and trade-ofs at all levels of the system architecture of networked sensors.the authors develop a post-SoC/32-bit design point called Hamilton, showing that using integrated components enables a ∼$7 core and shifts hardware modularity to design time. We design a system architecture, based on a tickless multithreading operating system, with cooperative/adaptive clocking, advanced sensor abstraction, and preemptive packet processing.

Abstract:

The emergence of low-power 32-bit Systems-on-Chip (SoCs), which integrate a 32-bit MCU, radio, and flash, presents an opportunity to re-examine design points and trade-ofs at all levels of the system architecture of networked sensors. To this end, we develop a post-SoC/32-bit design point called Hamilton, showing that using integrated components enables a ∼$7 core and shifts hardware modularity to design time. We study the interaction between hardware and embedded operating systems, identifying that (1) post-SoC motes provide lower idle current (5.9 µA) than traditional 16-bit motes, (2) 32-bit MCUs are a major energy consumer (e.g., tick increases idle current >50 times), comparable to radios, and (3) thread-based concurrency is viable, requiring only 8.3 µs of context switch time. We design a system architecture, based on a tickless multithreading operating system, with cooperative/adaptive clocking, advanced sensor abstraction, and preemptive packet processing. Its eficient MCU control improves concurrency with ∼30% less energy consumption. Together, these developments set the system architecture for networked sensors in a new direction.

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