Cycle stealing

In computing, traditionally cycle stealing is a method of accessing computer memory (RAM) or bus without interfering with the CPU. It is similar to direct memory access (DMA) for allowing I/O controllers to read or write RAM without CPU intervention. Clever exploitation of specific CPU or bus timings can permit the CPU to run at full speed without any delay if external devices access memory not actively participating in the CPU's current activity and complete the operations before any possible CPU conflict. Such systems are nearly dual-port RAM without the expense of high speed RAM. Most systems halt the CPU during the steal, essentially making it a form of DMA by another name.The cycle-stealing concept of the 1130permits the CPU program to start an operation on an I/O device and then continue the mainline program while the I/O device is performing its operation. Each I/O device that operates in this manner takes (steals) a cycle from the CPU when it is needed. In computing, traditionally cycle stealing is a method of accessing computer memory (RAM) or bus without interfering with the CPU. It is similar to direct memory access (DMA) for allowing I/O controllers to read or write RAM without CPU intervention. Clever exploitation of specific CPU or bus timings can permit the CPU to run at full speed without any delay if external devices access memory not actively participating in the CPU's current activity and complete the operations before any possible CPU conflict. Such systems are nearly dual-port RAM without the expense of high speed RAM. Most systems halt the CPU during the steal, essentially making it a form of DMA by another name. For example, a system with separate instruction and data memory banks can allow external devices one memory access to the data bank while the CPU was fetching an instruction from the instruction bank if both accesses are initiated simultaneously. A memory management unit is not essential, for example, the Zilog Z80's M1 line can be used to distinguish instruction from data access, so while the CPU is reading an instruction from instruction-RAM or ROM, the data RAM is available to other devices without interfering with CPU processing. Cycle stealing is difficult to achieve in modern systems due to many factors such as pipelining, where pre-fetch and concurrent elements are constantly accessing memory, leaving few predictable idle times to sneak in memory access. DMA is the only formal and predictable method for external devices to access RAM.