Subtractor

In electronics, a subtractor can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with an adder, in the general case of calculations on multi-bit numbers, three bits are involved in performing the subtraction for each bit of the difference: the minuend ( X i {displaystyle X_{i}} ), subtrahend ( Y i {displaystyle Y_{i}} ), and a borrow in from the previous (less significant) bit order position ( B i {displaystyle B_{i}} ). The outputs are the difference bit ( D i {displaystyle D_{i}} ) and borrow bit B i + 1 {displaystyle B_{i+1}} . The subtractor is best understood by considering that the subtrahend and both borrow bits have negative weights, whereas the X and D bits are positive. The operation performed by the subtractor is to rewrite X i − Y i − B i {displaystyle X_{i}-Y_{i}-B_{i}} (which can take the values -2, -1, 0, or 1) as the sum − 2 B i + 1 + D i {displaystyle -2B_{i+1}+D_{i}} . In electronics, a subtractor can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with an adder, in the general case of calculations on multi-bit numbers, three bits are involved in performing the subtraction for each bit of the difference: the minuend ( X i {displaystyle X_{i}} ), subtrahend ( Y i {displaystyle Y_{i}} ), and a borrow in from the previous (less significant) bit order position ( B i {displaystyle B_{i}} ). The outputs are the difference bit ( D i {displaystyle D_{i}} ) and borrow bit B i + 1 {displaystyle B_{i+1}} . The subtractor is best understood by considering that the subtrahend and both borrow bits have negative weights, whereas the X and D bits are positive. The operation performed by the subtractor is to rewrite X i − Y i − B i {displaystyle X_{i}-Y_{i}-B_{i}} (which can take the values -2, -1, 0, or 1) as the sum − 2 B i + 1 + D i {displaystyle -2B_{i+1}+D_{i}} . Subtractors are usually implemented within a binary adder for only a small cost when using the standard two's complement notation, by providing an addition/subtraction selector to the carry-in and to invert the second operand. The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend X {displaystyle X} and subtrahend Y {displaystyle Y} and two outputs the difference D {displaystyle D} and borrow out B out {displaystyle B_{ ext{out}}} . The borrow out signal is set when the subtractor needs to borrow from the next digit in a multi-digit subtraction. That is, B out = 1 {displaystyle B_{ ext{out}}=1} when X < Y {displaystyle X<Y} . Since X {displaystyle X} and Y {displaystyle Y} are bits, B out = 1 {displaystyle B_{ ext{out}}=1} if and only if X = 0 {displaystyle X=0} and Y = 1 {displaystyle Y=1} . An important point worth mentioning is that the half subtractor diagram aside implements X − Y {displaystyle X-Y} and not Y − X {displaystyle Y-X} since B out {displaystyle B_{ ext{out}}} on the diagram is given by This is an important distinction to make since subtraction itself is not commutative, but the difference bit D {displaystyle D} is calculated using an XOR gate which is commutative. The truth table for the half subtractor is: Using the table above and a Karnaugh map, we find the following logic equations for D {displaystyle D} and B out {displaystyle B_{ ext{out}}} :