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RISC-V (pronounced 'risk-five') is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. As of March 2019, version 2.2 of the user-space ISA is frozen, permitting most software development to proceed. The privileged ISA is available as draft version 1.10. A debug specification is available as a draft version 0.13.1. Usable new ISAs are usually very expensive. Computer-designers normally cannot afford to work for free. Also, developing a CPU requires design expertise in several specialties: electronic digital logic, compilers, and operating systems. It is rare to find such a team outside of a professional engineering organization. The team is normally paid from money charged for their designs. Therefore, commercial vendors of computer designs, such as ARM Holdings and MIPS Technologies charge royalties for the use of their designs, patents and copyrights. They also often require non-disclosure agreements before releasing documents that describe their designs' detailed advantages and instruction set. In many cases, they never describe the reasons for their design choices. This expense and secrecy make the development of new hardware and software much more difficult. It also prevents security audits. Another result is that modern, high-quality general-purpose computer instruction sets have not been explained or available except in academic settings. RISC-V was started to solve these problems. The goal was to make a practical ISA that was open-sourced, usable academically and in any hardware or software design without royalties. Also, the rationales for every part of the project are explained, at least broadly. The RISC-V authors are academic but have substantial experience in computer design. The RISC-V ISA is a direct development from a series of academic computer-design projects. It was originated in part to aid such projects. To address the cost of design, the project started as academic research funded by DARPA. In order to build a large, continuing community of users and therefore accumulate designs and software, the RISC-V ISA designers planned to support a wide variety of practical uses: Small, fast, and low-power real-world implementations, without over-architecting for a particular microarchitecture. A need for a large base of contributors is part of the reason why RISC-V was engineered to fit so many uses.

[ "Field-programmable gate array", "Architecture", "Instruction set", "Coremark" ]
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