OpenRISC

OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computing (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community. OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computing (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32- and 64-bit processors with optional floating point and vector processing support, and the OpenRISC 1200 implementation of this was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL). The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL). A reference system on a chip (SoC) implementation based on the OpenRISC 1200 was developed, named the OpenRISC Reference Platform System-on-Chip (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on field-programmable gate arrays (FPGAs), and there have been several commercial derivatives produced. The instruction set is a reasonably simple MIPS architecture-like traditional RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors. Another notable feature is a rich set of single instruction, multiple data (SIMD) instructions intended for digital signal processing. Most implementations are on field-programmable gate arrays (FPGAs) which give the possibility to iterate on the design at the cost of performance. As the OpenRISC 1000 is now considered stable, ORSoC (owner of OpenCores) launched a crowd-funding project trying to build a cost-efficient application-specific integrated circuit (ASIC) to get improved performance. ORSoC faced criticism for this from the community. The project never reached the goal. As of April 2017, no open-source ASIC had been produced.