Globally asynchronous locally synchronous

A GALS circuit consists of a set of locally synchronous modules communicating with each other via asynchronous wrappers. Each synchronous subsystem ('clock domain') can run on its own independent clock (frequency). Advantages include much lower electromagnetic interference (EMI). The CMOS circuit (logic gates) requires relatively large supply current when changing state from 0 to 1. These changes are aggregated for synchronous circuit as most changes are initialised by an active clock edge. Therefore, large spikes on supply current occur at active clock edges. These spikes can cause large electromagnetic interference, and may lead to circuit malfunction. In order to limit these spikes large number of decoupling capacitors are used. Another solution is to use a GALS design style, i.e. design (locally) is synchronous (thus easier to be designed than asynchronous circuit) but globally asynchronous, i.e. there are different (e.g. phase shifted, rising and falling active edge) clock signal regimes thus supply current spikes do not aggregate at the same time. Consequently, GALS design style is often used in system-on-a-chip (SoC). It is especially used in Network-on-Chip (NoC) architectures for SoCs.