Voltage droop reduction for multiple-power domain SoCs with on-die LDO using output voltage boost and adaptive response scaling

Low power techniques such as clock gating and dynamic frequency scaling cause a sudden surge in power supply current. To reduce the voltage droop induced by such a surge in the load current of an LDO regulator, we propose output voltage boost and adaptive response scaling techniques that utilize clock activation detection. Measured results from a test chip fabricated in 65-nm CMOS technology show that a combination of the two techniques reduces the worst-case output voltage droop by 63% compared to operation without them. This results in a voltage offset reduction from 45% to 15%, which leads to 20% power savings.