Acceleration of MPEG-4 video applications with the reconfigurable HW processor XPP

The next generation of mobile phones need high computational power to fulfil their primary tasks, multimedia applications and services. To achieve this goal, powerful processors with high clock frequencies are used. Although the processing power capabilities are increased, the capabilities in the electrical power supply are not. The results are powerful mobile devices with insufficient batteries. The formula: higher frequency is equivalent with a higher computational power is still valid, but for the price of a high power consumption. One solution is the usage of specialized and therefore more compact hardware, like ASICs, DSPs etc. On the other side this will greatly reduce the flexibility of the device and the application areas will be limited. New technology approaches have to be found to reduce these dilemmas. This paper describes an ongoing study of a SoC design where the reconfigurable coprocessor XPP is embedded with a standard mobile phone processor. The target application for this system is a low-cost/power environment running a MPEG-4 encoder/decoder (Visual Profile: Simple@L1). The whole MPEG-4 encoding/decoding process is partitioned between the standard processor, which is controlling the system and executes control-intensive algorithms, and its XPP coprocessor, which executes the computational-intensive data-flow algorithms and sends the results back to the host processor or a shared memory bank.