High-performance arithmetic circuits for the counter cmos image sensor configurations and applications

The present invention relates to a circuit for arithmetic counter high-performance CMOS image sensors, configuration and application. The arithmetic counter circuit for a high performance CMOS image sensor comprising: a plurality of flip-flops of a plurality of counter stage; and a plurality of multiplexers of said plurality of counter stages, coupled to said plurality of flip-flops . Each of the plurality of multiplexers coupled to receive a control signal, said control signal comprises a binary trigger signal, the hold signal, the shift enable signal pattern or at least one signal. The control signal selects the output of each of the plurality of multiplexers. Each of the plurality of flip-flops coupled to the plurality of multiplexers based on the input received toggles in state, holding state, the set state or a reset state of one. Other embodiments are described.