Half Swing Clocking Scheme at 45nm

Achievement of high processor speed with low power consumption is an elemental factor in processor technology, especially for hand-held devices. The need for low power has caused a major paradigm shift where power dissipation has become a important consideration as performance and area. In CMOS circuits, dynamic power consumption is proportional to the transition frequency, capacitance, and square of supply voltage. Consequentially, lowering supply voltage delivers significant power savings compromising the speed of processor. Large portion of the total power is consumed in the clocking circuitry in embedded processor technology. So clock power can be reduced using half swing of clock scheme which will cut down the power dissipation and minimum speed degradation. In Digital circuits by using double-edge triggered flip flops (DETFFs), the clock frequency can be significantly reduced ideally, in half while preserving the rate of data processing. Using lower clock frequency may translate into considerable power savings for the clocked portions of a circuit, including the clock distribution network and flip-flops. The designing is based on 45nm process technology.