Gated silicon nanowire for thermo-electric power generation and temperature sensing

Gate-all-around Si FETs are predicted to be the future of integrated CMOS circuits (ICs). The reduction in size of the Si channel, surrounded by oxide and a gate causes increased self-heating effects due to a reduction in thermal conductivity of the Si channel. Although, this degrades performance, we demonstrate that this can be exploited for localized thermoelectric power generation and temperature sensing that help reduce energy waste and increase IC lifetime. We show, using Sentaurus TCAD simulations, that unbiased gated intrinsic Si nanowires (NWs) can generate 2.2 times higher output power than doped nanowires by choosing the correct metal gate work function. In addition, the voltage on the gate of the nanowire can be used to sense the temperature at the hot-spot in gate-all-around ICs. Among the studied gated NWs, the double gated (DG) structure with 30 nm gate length shows higher sensitivity to the change of temperature.