Dual-gate Amorphous Thin Film Transistors for Electrophoretic Display Response Speed Optimization

Dual-gate structure with a common gate design is applied to amorphous silicon transistors (a-Si TFTs) for the first time, to solve the problem of slow response speed of electrophoretic display (EPD), by regularizing the over-ranged drain-source leakage currents under high voltages. In this paper, the dual-gate structure's effects of reducing the off-state leakage current while seldom lowering the on-state current is predicted by theoretical analysis comparing with the single gate a-Si TFT. The SPICE simulation results prove that dual-gate structure can reduce about half of the leakage current. In order to evaluate the effect of response time reduction, this paper establishes a compact model of the response time t and leakage current Ioff. According to the Matlab simulation, one can find the response time is shorted from 380 ms to 320 ms when the leakage current is 20 pA, and from 530 ms to 360 ms when the leakage current is 35 pA, indicating a rising in frame rate from 2 Hz to 3 Hz. At last, basing on the t-Ioff model, this paper points out that reducing the radius of electrophoretic particle or using a larger storage capacitor are also crucial for EPD's response time optimization.