Simulation of Daisy Chain Flip-Chip interconnections

Flip-chip interconnection technologies have been tested through the use of a test chip with embedded single-bump daisy chains. The Flip-Chip technologies are selected among Au bump thermocompression (TC) with and without NCA underfiller, anisotropic conductive adhesive (ACA) bonding, and AuSn20 eutectic solder. The single bumps were then measured with a high precision resistance meter and compared between them to check the electrical behavior of different interconnection technologies. Simulation with Comsol helped to provide a more accurate estimation of the bump resistance, calculating a correction factor to the classical 4- probe measurement scheme expectations. This correction factor was also experimentally measured and is mainly caused by current and voltage path asymmetries arising from the bump routing layout and its 3D geometrical features. The FEM model allowed normalizing results for measured resistances among different pads within the same daisy chain chip.