Evaluating Cell Library Sizing Methodologies for Ultra-Low Power Near-Threshold Operation in Bulk CMOS

A systematic evaluation of different transistor sizing methodologies for near-threshold (NTV) operation of CMOS standard cell libraries is presented herein. The methodologies are developed to correlate different library design optimizing goals, such as area, maximum attainable frequency, energy consumption, and symmetric transition slews. Consideration is given to optimizing NTV cells for the Minimum-Energy V DD supply for a bulk 40 nm CMOS technology. Sizing is optimized for a small set of cells (NOR, NAND, and inverters at three different drive strengths), and energy, delay, and area results compared against a commercial cell library. Our results establish the best W pmos /W nmos ratio for each defined trade-off (energy-delay, area-delay, slew-rates) while operating at a low-supply, around 300 mV. This voltage enables the maximum energy efficiency for logic in the 40 nm CMOS technology considered. The proposed method can be applied to any CMOS technology, as our results establish the methodology as a simple approach to enhance energy efficiency for NTV.