Digital control scheme for robust clock tuning and PWM phase synchronization in digitally controlled multi-POL applications

This paper describes a novel clock tuning and subsequent PWM phase synchronization scheme for digitally controlled switching power converters. Its architecture and circuit blocks are presented and explained in detail. The scheme has been implemented in a commercially available digital controller integrated circuit (IC) using a standard CMOS process. Experimental results from a multi point-of-load (POL) application are presented.