10 nm TriGate High k Underlap FinFETs: Scaling Effects and Analog Performance

Nano scale devices with improved performance than the conventional CMOS devices is of great need in recent days. The paper investigates the performance of 10 nm Trigate FinFET structure with high k dielectric spacer on either side of the channel in the underlap region. The proposed structure increases the On-Off ratio (ION/ IOFF) of drain current by order of 106 and also improves the subthreshold swing (SS). Further, it enhances the transconductance (gm) at the low gate voltage, raises the output conductance (gd) and intrinsic gain (gm/gd) proving that the device provides efficient analog performance suitable for RF applications.