The polybus: A flexible and fault-tolerant multiprocessor interconnection

Abstract Polybus is a general purpose multiprocessor bus system which links modules such as processors, memories and input-output devices in a homogeneous way. It is a multiple common bus consisting of an arbitrary number of busses capable of independent operation. Connected modules, however, access the Polybus system like a single common bus. The multiple bus structure is user transparent, i.e busses may be added or removed without hardware or software modifications. The bus bandwidth can therefore be adjusted to actual requirements. Transfer speeds of up to n × 12 Mbytes s −1 (where n is the number of busses used) can be achieved. Circuit switching through the bus system is managed by a decentralized arbiter which allows access according to priority as well as fair treatment of requests. Random assignment of busses to requests enables automatic by passing of faulty paths by re-try. Several addressing modes allow access to specific modules, to pools of modules or to an arbitrary member of a pool. This supports multiprocessor-transparent programming as well as data flow applications. In this paper an overview of the Polybus system, details of its operation and a comparison of some implementation details with other standard solutions are presented.