HCS degradation of 5 nm oxide high-voltage PLDMOS

Abstract Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage ( V GS ) and high drain voltage ( V DS ), reduction of the ON-resistance ( R ON ) is observed. At stress times at which R ON almost reaches its constant level, an increase of the drain leakage in OFF state ( V DS  = −60 V, V GS  = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.