Rapid RCLK modeling of on-chip passives and interconnects with efficient K reduction and passivity enforcement

An RCLK modeling technique has been proposed for intended and parasitic inductance in silicon ICs, providing rapid extraction times. To tackle netlist size and passivity issues, passivity enforcement techniques are presented in this article based on eigenvalue decomposition and bandwidth reduction of the inductance matrix. Runtime performance of the RCLK modeling method is reported for the first time, applied to realistic 65 nm CMOS circuits, while the computational overhead of passivity enforcement is given. The proposed techniques can reduce netlists between 41% and 96% in the cases presented, while runtimes for passivity enforcement can be improved by 85% or better, compared with eigenvalue decomposition of a full inductance matrix. These results indicate that full inductance modeling of silicon circuitry becomes practical, resolving the bottleneck facing other known electromagnetic simulation methods. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2012.