Physically Unclonable Function: Design of a Silicon Arbiter-PUF on CMOS 65nm

This chapter addresses some of the practical difficulties when designing a silicon-PUF based on CMOS technology. When designing such a PUF, and particularly in the case of an arbiter-PUF, particular care should be taken during the place and route phase. To ensure the properties of the PUF, full-custom back-end design may be required. This chapter give details on the design phase considering the example of an arbiter-PUF made of several switch boxes. Each of them can be configured by the challenge, and an arbiter (NAND2 – RS-latch) to decide of the output of the PUF. The technology node targeted for the ASIC implementation is the CMOS 65 nm.