Old Web
English
Sign In
Acemap
>
Paper
>
100 Gb/s Data Link Layer - from a Simulation to FPGA Implementation
100 Gb/s Data Link Layer - from a Simulation to FPGA Implementation
2016
Ł. Łopaciński
Marcin Brzozowski
R. Kraemer
Steffen Buechner
Joerg Nolte
Keywords:
Hybrid automatic repeat request
Field-programmable gate array
Link adaptation
Data link layer
Frame aggregation
Computer network
Computer science
Computer architecture
Segmentation
Correction
Source
Cite
Save
Machine Reading By IdeaReader
16
References
1
Citations
NaN
KQI
[]