Contactless Test Access Mechanism for TSV-Based 3-D ICs Utilizing Capacitive Coupling

Through silicon via (TSV) is considered an enabling technology for 3-D integrated circuit (IC) integration. Testing 3-D ICs with multiple stacked dies is a challenging task. Probing a TSV for the purpose of testing with conventional wafer probes can undermine its physical integrity. In this paper, a contactless TSV probing method using capacitive coupling is presented. The proposed solution eliminates the risks of direct TSV probing and supports the high-density and fine-pitch requirements for TSV probing. 3-D full-wave simulations indicate that a strong electric field is formed between the probe and the TSV when the distance between them falls below 5 $\mu \text{m}$ . The measurement results on a prototype fabricated with CMOS 65-nm technology show that the proposed TSV probing scheme presents a −55-dB insertion loss at 1-GHz frequency. The probe can be used up to a data rate of 5 Gbits/s while maintaining higher than 35-dB signal-to-noise ratio.