Ka-Band Stacked Power Amplifier on 22 nm CMOS FDSOI Technology Utilizing Back-Gate Bias for Linearity Improvement.

This paper presents a method for extending millimeter wave power amplifier (PA) linear range by fine tuning the CMOS SOI device output characteristics via back-gate biasing. The effect of back-gate biasing to PA performance is measured and reported. It is demonstrated how implementing the same bias point with different back-gate values affects the linear range of the fabricated PA. By applying positive back-bias to the NFET devices, the measured PA displays minimum AM-PM and reaches maximum output power, PAE and 1 dB compression point of 16.3 dBm, 23 % and 13.9 dBm, respectively. EVM of 6.8 % and ACLR of −29.3 dBC were achieved at 5 dBm average output channel power with a 100MHz 64-QAM OFDM signal.