Quantitative Projections of the Cost Benefits of 3D Integration

The traditional drivers for the adoption of 3D integration technology are footprint, power, performance, and/or bandwidth gains at the expense of increased cost due to additional wafer processing, dies stacking and 3D test. However, for larger dies in cutting edge technology, total system cost can be reduced by leveraging heterogeneous 3D stacking, if it is done correctly. This paper presents a model which allows comparing the cost of moving a traditionally designed chip at given advanced node (in 2D) to an implementation in the next generation technology node using heterogeneous face-to-face 3D stacking. With this model we show that 3D integration scheme can be driven by cost savings. This is possible in a world where CMOS cost per transistor continues to improve because other components that are required in large SoCs, notably analog and I/O functionality, do not. The proposed model is used to evaluate the cost impact of iterating a 14nm SoC into a 10nm SoC (traditional scaling) compared to a 3D impleme...