Single Metal Gate on High-k Gate Stacks for 45nm Low Power CMOS

We present a low cost, single metal gate/high-k gate stack integration, which provides a very high performing NMOS coupled with a counter-doped PMOS for a 45nm low power (LP) CMOS technology. Inversion T ox (T inv ) values of 16Aring/18Aring (NMOS/PMOS) result in gate leakage current densities of 0.1/0.01 A/cm 2 and enable self-heated drive currents of 850/325muA/mum at 1nA/mum off-state leakage and V dd =1V (900/340muA/mum non-self-heated). Additionally, the NMOS drive current of 1550 muA/mum (1650muA/mum non-self-heated) at an I off = 100nA/mum and V dd =1.2V is the highest reported for a hafnium-based high-k gate stack. The approach is compatible with a dual-gate oxide (DGO) module for I/O devices and allows optimization for performance and power typically only possible in triple gate oxide architectures