Optimized AreaandOptimized SpeedHardware Implementations ofAESonFPGA

TheAdvanced Encryption Standard (AES)isthelast standard forcryptography andhasgained widesupport asmeanstosecure digital data. Inthis paper, Tradeoffs ofspeed vs.area that areinherent inthedesign ofasecurity processor areexplored. Twoimplementations oftheAESonXilinx Virtex 4FPGAare introduced, thefirst design iscalled optimized area AESwhichisbased onthe basic architecture oftheAES,thesecond oneiscalled optimized speed AESwhich isbased onthesub-pipelined architecture oftheAES.AnAEScrypto processor withserial interface wasimplemented anditcould beusedwithanyofour designed encryptor ordecryptor.