Modeling and hardware correlation of power distribution networks for multi-gigabit designs

This paper presents simulation and measurement results for package and board power distribution systems of a low cost multi-gigabit design. A modeling methodology aimed to model the entire power distribution system across three different hierarchies of the system from the PCB to the package and to on-chip circuits in a single model is presented. Using this model system trade-offs are demonstrated in the design of the power distribution system of a high-speed memory interface.