A sigma-delta based square-law compandor

A compandor (compressor and expander) architecture for telecom applications is discussed. It reduces the number of off-chip components and allows full transceiver signal paths to be integrated and operated from a single supply as low as 3 V. Measured dynamic range is greater than 60 dB, with noise and distortion less than 57 dB. Both the 3 V and 5 V versions were implemented in a 2 mu m, double-poly, double metal CMOS process. The compressor and expander occupy the same die area: 2.5 mm/sup 2/ each. The only off-chip components are value insensitive: two DC blocking capacitors. >