Analyzing and Increasing Yield of ZnO Thin-Film Transistors for Large-area Sensing Systems by Preventing Process-Induced Gate Dielectric Breakdown

Thin film transistors (TFT's) on flexible large-area substrates enable large-scale deployment of form-fitting embedded and tactile sensors. However, the combination of insulating substrates (e.g., glass, plastics), long metal traces for distributed sensors and circuits over large areas, plasma processing and packaging/assembly for hybrid (CMOS-TFT) systems makes anomalous breakdown in TFT gate dielectrics a prominent limiter of yield in complex systems. In this work, we use layout modifications, shielding layers, and temporary “shorting bars” to enable high-yield processing and assembly of distributed sensor-acquisition circuits, in which 161 ZnO TFT's are used per sensor (Fig. 1) to implement compressed sensing (i.e., matrix projection). Although this is a large number of TFT's, compressed sensing greatly enhances critical system metrics, e.g., reduces the number of acquisition cycles and physical interfaces to a readout CMOS IC, as demonstrated in a tactile force-sensing system [1].