Memory array and methods of operating and manufacturing methods

Discloses a method of operating a memory array and its manufacturing method. An example memory array may include: disposed in a matrix to form a plurality of arrays based on the selection transistor of the first nanowire; and a plurality of memory cell layers stacked on the array selection transistor, each memory cell comprises a select transistor array layer phase corresponding resistive-switching device array. Resistive device may include a second nanowire, a second resistive material layer around the nanowires, and the winding layer becomes an electrode material layer constituting the MIM configuration. The memory array may further comprise: a plurality of select lines, each select line electrically connected to a corresponding row selection transistor; a plurality of bit lines, each bit line is electrically connected to one end of a respective one selection transistor, each of the select transistor other are electrically connected to an end of an adjacent memory cell in a respective layer of a second resistive nanowire device; a plurality of word lines, each word line is electrically connected to the electrode layer of the corresponding memory cell layer.