Investigation of cutting edge in edge-on silicon microstrip detector

Abstract Investigation of cutting edge properties in edge-on silicon microstrip detector has been performed. An advanced approach for reducing dead layer thickness has been introduced. It consists of standard wafer sawing through entire wafer thickness, followed by dry chemical etching and thin layer passivation of the cutting surface. Proposed approach is developed in such a way that no additional photolithographic process steps and critical handling with individual chips are needed after detector fabrication. Results presented in the paper show that this approach results in effective reduction of cutting edge thickness down to 50 μm. Such reduction of dead layer thickness, together with applied efficient current termination technique resulted in substantial improvement of detector structure performance. By described optimization of detector dead layer thickness, detection efficiency has been improved up to 15%.