Optimization of porous ultra low-κ dielectrics (κ ≤ 2.55) for 28nm generation

There is an ongoing need in the microelectronics industry to increase circuit density in multilevel back-end-of line (BEOL) interconnects to improve the operating speed and reduce power consumption. One way to maintain capacitance-resistance (RC) performance, without de grading yield or reliability is through introduction of porous ultra low-κ materials (ULK) as interlevel dielectrics (ILD). This paper presents the ability to tune ULK films through simple processing optimization steps to meet the specific integration requirements. Balancing composition of the film to minimize damage needs to be coupled with improving mechanical integrity for packing compatibility.