A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders

This paper presents a novel discrepancy computationless RiBM (DcRiBM) algorithm and its architecture for decoding BCH codes. The DcRiBM algorithm allows elimination of the discrepancy computation control block and reduced hardware complexity as compared to conventional RiBM algorithm architecture. The low-complexity DcRiBM architecture has been designed architecture. The low-complexity DcRiBM architecture has been designed and implemented with 0.18-mum CMOS standard cell technology in a supply voltage of 1.8 V. The BCH(2040,1930) decoder with the proposed architecture operates approximately 2.9 Gb/s at a clock frequency of 265 MHz and has approximately 32% fewer gate counts than the conventional RiBM architecture.