A Current Spike Reduction Method for Totem-pole Bridgeless PFC at Zero-crossing

Totem-pole bridgeless Power Factor Corrector (PFC) converter is a promising topology after the emerging of the wide-band-gap (WBG) semiconductor devices. However, the inherited current spike at zero-crossing in this topology is a challenge for low current harmonics and high power factor. This paper, based on the circuit topology, analyzes a generation mechanism of the current spike. The influence of phase delay caused by power inductor between the AC voltage and the required full bridge output voltage is illustrated by mathematical calculation. Then a method that using the zero-crossing points of the control loop output instead of AC voltage’s as control signal of the low frequency (LF) leg is proposed. Finally, the experimental measurements are given to verify the effectiveness of the proposed method in a 1kW totem-pole PFC converter prototype.