PolyPC: Polymorphic parallel computing framework on embedded reconfigurable system

With the help of parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance of many applications. However, designers are typically required to have excellent hardware programming skills and unique optimization techniques to fully explore the potential of FPGA resources. In this work, we propose the PolyPC (Polymorphic Parallel Computing) framework that aims to improve productivity while achieving performance speedup. The PolyPC framework implements a custom hardware platform on which the PolyPC framework extends vendor-provided tools to convert OpenCL-like programs into executables by using highlevel synthesis (HLS) tools. The PolyPC framework is evaluated regarding performance, area efficiency, and multitasking. The results show a maximum of 66 folds of speedup over a dual-core ARM processor, and 1,043 folds of speedup over a high-performance MicroBlaze soft processor, with 125 folds of area efficiency. In addition, it delivers a significant improvement in response time to high-priority PolyTasks with the priority-aware scheduling.