Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs

Faithfully truncated adders are used for low cost FIR implementations in this paper, which improves state-of-the-art CSD-based FIR filter designs for further area and power reduction while meeting the accuracy requirement. As a solution to the accuracy loss caused by truncated adders, this paper performed a static error analysis of truncated adders. Furthermore, based upon our mathematical analysis, we show that, with a given accuracy constraint, an optimal truncated adder configuration can be effortlessly determined for area-power efficient FIR designs. Evaluation results on various FIR designs showed that 16.8%∼35.4% reduction in area and 11.8%∼27.9% in power saving can be achieved with the proposed optimal truncated adder designs within an average error of 1 ulp.