Reliability-aware design space exploration for fully integrated RF CMOS PA

A design for reliability approach is proposed for fully integrated RF CMOS class A-to-C power amplifiers. Reliability hazards like time dependent dielectric breakdown and hot carrier injection are mapped into the design space, including the expected parametric degradation of the circuit, by fitting widely accepted models to experimental degradation results on the target technology. A prototype amplifier was used to validate RF degradation models and their impact on the output power degradation under accelerated stress. The methodology is based on a design space exploration of the highest efficiency designs attainable in a target technology. Electrical characteristics of passives and transistors are considered through look-up tables. The proposed approach allows to reduce the full universe of available designs to those that are specification and reliability compliant, avoiding a simulator-in-the-loop approach. A test case for a 3 dBm output power amplifier from the design space shows good agreement between predictions and SPICE simulations, including projected parametric degradation due to hot carrier injection.