3D Wafer Level Packaging: Processes and Materials for Trough Silicon Vias & Thin Die Embedding

In modern electronics, heterogenous system requirements may vary due to the different form factors of the individual dies, the required interconnects pitch and dimensions are changing accordingly, 3D Wafer Level Packaging (3DWLP) offers the opportunity to address these needs. We report on key technological building block for 3D integration of Si dies at post-passivation level. We report both on system-in-package (SiP) type TSVs — addressing the needs for heterogeneous system integration such as 3D-SiP and interposers with pitch > 100 μm — and IC scaling Through Silicon Vias (TSV). The dimensions of the latter are aiming at pitch <50 μm for Si thickness of 50 μm following the IC bond-pad scaling roadmaps. The 3DWLP TSV process is performed after back grinding the Si and realizes a contact to the bottom layer of the device stack. A specific aspect of the proposed flows is the use of a polymer as a dielectric layer between the TSV metal and the silicon allowing for stress buffering and low parasitic capacitance of the TSV structure. Alternatively, increasing demand for form factor and increased functionality can be met trough stacking and embedding of extremely thin dies (<20μm) at wafer level. The embedding build-up is composed of photosensitive polymer and copper plated metal films. Successful embedding of 20 μm thick Si dies as well as their reliability short-comings are shown. In both cases, the key technological building blocks consisting of the use of temporary wafer bonding, wafer thinning, high throughput bonding, microbumping technologies and the use of semi-additive Cu plating for via and redistribution layer metallization.