A 12-bit 800 MS/s Dual-Residue Pipeline ADC

This paper presents the design of a pipeline analog-to-digital converter (ADC) based on the dual-residue principle. By applying this technique, the ADC becomes insensitive to the exact gain of the MDAC residue amplifiers. This allows these amplifiers to be designed with a relatively low open-loop gain and low bandwidth, which is favorable for the power consumption of the ADC. The offsets of the residue amplifiers, however, limit the accuracy of the ADC. Therefore, offset calibration is required for the ADC to achieve a high resolution.