HDTV level MPEG2 video decoder VLSI
1995
A novel architecture for an HDTV level MPEG2 decoder is developed, which consists of specific functional macrocells and macroblock level pipeline buffers. Owing to the sophisticated I/O interface among macrocells, macroblock level pipeline buffers are successfully incorporated with functional macrocells. A new organization of frame memory and interface is also devised. The designed decoder contains 454 K transistors, and occupies 81.0 mm/sup 2/ with a 0.6 /spl mu/m triple-metal CMOS technology.
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