Study on Extraction of Capacitance Parameters of Three Dimensional Interconnect Structures Based on Finite Element Method

In recent years, the rapid development of industry makes the proportion of interconnect in chip increase rapidly. In order to ensure the stability and reliability of the circuit, accurate 3D modeling and high efficiency parasitic parameter extraction are needed for the chip interconnect. This paper has carried out the research on the extraction of capacitance parameters of the 3D finite element interconnection line. Starting from the principle of multi-conductor capacitance calculation, the problem is reduced to solving the Laplace equation for point boundary conditions. By using the finite element method (FEM), the solving process is analyzed and deduced. In addition, based on the high-efficiency parallel support software framework JAUMIN, this paper realizes the parallel calculation of the three-dimensional finite element capacitance parameter extraction, which greatly improves the calculation efficiency. Finally, the algorithm is applied to a representative interconnect structure. The calculation results are compared with the multi-physics commercial simulation software COMSOL. The results show that the potential distribution diagram is consistent.