Electronic input or output buffer circuit having MOS transistor having a plurality of loop-shaped cells

Electronic input or output buffer circuit which is formed on a semiconductor substrate and a MOS transistor having a plurality of cells, each cell comprising: - a first circuit portion (43) which is formed as a loop; - a second circuit portion (41) which is in the first circuit region (43) and disposed separately therefrom; and - a third circuit section (42) which is formed as a loop and between the first and second circuit portions (43, 41) is arranged to the first and second circuit portions in a first operating state (43, 41) to each other, and second in a operating state, the first and second circuit portions (43, 41) to separate.