A 0.18 /spl mu/m 256 Mb DDR-SDRAM with low-cost post-mold-tuning method for DLL replica

A delay-locked loop (DLL) must have a large delay line to work over a wide range of frequency. This makes the layout area larger. A hierarchy delay line solves this problem. But coarse and fine delay changing at the same time causes jitter. This DLL and voltage down converter (VDC) avoids the jitter problem.