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New polysilicon disposable sidewall process for sub-50 nm CMOS
New polysilicon disposable sidewall process for sub-50 nm CMOS
2001
K-L. Lee
Diane C. Boyd
J. Brancaccio
J. Bucchignano
Jin Cai
Kevin K. Chan
Hussein I. Hanafi
P. Kozlowski
R. J. Miller
R. A. Roy
Leathen Shi
E. Sikorski
M. Surendra
Shalom J. Wind
Qingyun Yang
J Yoon
Chienfan Yu
Y. Zhang
Yuan Taur
Keywords:
Analytical chemistry
Annealing (metallurgy)
Chemical vapor deposition
Materials science
Electronic engineering
Boron
CMOS
Doping
Microelectronics
STRIPS
Etching
Correction
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