A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array

A $33,464 \mu \mathrm {m}^{2}$ GZIP decompression accelerator is fabricated in 14nm CMOS, achieving industry-leading 20.5Gbps throughput. The design features out-of-order speculative Huffman decoder to break the fundamental serial dependency resulting in 69% higher decode throughput. The hybrid dual-path decoder provides $2.3 \times $ higher performance with multi-write enabled register-file array increasing decompression throughput by up to 41%. The arithmetic-architecture-circuit co-optimized design operates at 1.4GHz at 750mV, $25 ^{\circ}\mathrm {C}$ with peak measured energy-efficiency of 1.86pJ/code at 280mV, $2.7 \times $ higher than previously reported implementations.