Strain state in silicon structures for microprocessor technology

A promising approach to improve the performance of present CMOS devices is to introduce mechanical strain into the channel regions below the transistor gates. Strain can be generated as global strain on the whole wafer level (e.g., by growing strained silicon films on strain-relaxed silicon–germanium (SiGe) alloy layers or by using strained silicon films on an insulator), or as local strain on the transistor scale by applying specific technology processes (e.g., making use of embedded SiGe source-drain regions). The detection of strain in very thin silicon films requires sophisticated techniques with high depth sensitivity, whereas the measurement of the local strain state in thin Si structures with small lateral dimensions below 50 nm – such as the channels of current CMOS transistors – still remains to be mastered. A technique possessing the potential for solving this problem is Raman spectroscopy, where the diffraction limit for lateral resolution can be bypassed by near-field approaches. In the present paper, the occurrence of large strains in SiGe films and corresponding stresses in the GPa range are demonstrated by Raman spectroscopy, utilizing a simple approach for determining strain and composition separately. To estimate the strain distribution in a silicon channel structure due to embedded SiGe source–drain regions, a silicon strain calculation is applied based on a continuum-mechanical model utilizing a continuous distribution of virtual dislocations along the Si–SiGe boundaries. Within the framework of this model, the stress state in a 2D approximation is obtained by analytical expressions. Thus, the spatial distribution of channel strain and the impact of geometry on the strain state are obtained in a straightforward way.