Inductively coupled plasma etching of tapered via in silicon for MEMS integration

(Upper) Illustration of MEMS 3D integration and wafer-level packaging with a typical TSV technology; (lower left) schematic of an ICP etch system; (lower right) a 50µm via with 72? profile by means of ICP etch.Display Omitted Tapered TSV etching.Monotonic profile angles.Smooth sidewall. An ICP plasma etching technique for fabrication of tapered vias on silicon substrates has been developed by means of single patterning and etching process. Experimentally, effects of parameters including ICP power, chamber pressure, gas ratio and RF bias power were investigated for their impact on etch rate, selectivity, profile and surface roughness. Monotonic profile angles in the range of 60-80? have been achieved on 10-50µm wide vias through adjustment of the C4F8/SF6 ratio and optimization on other key parameters. We found that addition of O2 controlled lateral etch rate only weakly, except when running the process at cryogenic temperature. Adjustment of the process powers was a significant factor in controlling sidewall roughness.