Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application

Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson's equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 $\mu \hbox{m}$ . After presenting the fundamental $C$ – $V$ characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window ( $\vert{V}_{\rm ow}\vert=\hbox{20}\ \hbox{V} $ ) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge $Q_{\rm ot} $ engineering in TSV oxide liner, neither considerations of the ${V}_{\rm FB} $ shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.